1. Field of the Invention
This invention relates generally to molded dual in line packages (DIPs) and fabrication methods therefor, and more particularly to DIPs and fabrication methods therefor having semiconductor or integrated circuit chips mounted thereon and wire bonded thereto.
2. Description of the Prior Art
In the past, semiconductor devices were initially made and packaged by electrically connecting each chip containing a semiconductor device to a substrate having a printed circuit or conductive pattern thereon. These early forms of packages generally had passive (i.e. resistors, capacitors, etc.) devices located on the substrate and became known as hybrid circuits because of the combination of semiconductor and nonsemiconductor types of devices on a single substrate. Generally, the substrate that was used for the package was an insulator made of, for example, ceramic or glass. The semiconductor chip was either mounted face down ("Flip-Chip") or face up. In the face up type of mounting, electrically conductive leads were connected, such as by wire bonding, to specific conductors of the pattern of conductors located on the substrate. In the Flip-Chip type of mounting, the semiconductor chip was electrically and mechanically connected such as by solder bumps to soldered regions electrically connected to conductors located on the substrate.
As the semiconductor technology developed, lead frame DIPs were created and used as a means of providing packages for semiconductor integrated circuit (IC) chips. These DIPs were ideal to use as packages for IC chips because they could be manufactured in high volume at relatively lower cost than previous types of packages. To complete the package, plastic was formed in a plastic molding operation about portions of the lead frame including the IC chip to provide an encapsulation therefor.
Although molded lead frame DIPs are non-hermetic, they offer certain significant advantages. First, they can be manufactured at a very low cost and are machine insertable. Second, their leads are accessible from the top which facilitates testing and monitoring of certain functions. As a result, molded lead frame DIPs have become widely accepted in the marketplace.
Unfortunately, prior art molded lead frame packages suffer certain serious disadvantages. Integrated circuit electronic parameters shift during molding due to pressure and other interactions with the molding epoxy. High yield losses of sensitive or complex chips are probably due to the flow of molding epoxy and contact with the chips and wire bonds. Integrated circuit performance shifts and wire bond degradation are possible due to the relatively high molding temperatures (300.degree. C. to 400.degree. C.) to which the integrated circuits are exposed. Furthermore, many chips in such packages tend to degrade in performance or fail entirely over a period of time.
Since the leads are shorted together in the lead frame until molding is completed, the completed package cannot be tested until molding is complete. However, when the molding operation is completed and the lead frame cut to provide the completed DIP for testing, it is virtually impossible to do anything further to the chip located within the molded plastic encapsulator. For example, a very expensive chip which has only a single broken lead can not be repaired without the laborious job of delicately cutting apart the encapsulation. Cutting apart the encapsulation to get to the chip for repair is not very practical to say the least, especially in view of the danger of creating more damage to the chip.
Furthermore, integrated circuits mounted upon open lead frames must be handled by molding personnel who may create damage to the chip, bonds or package during such handling. More time and care are required for loading the molds, and higher operator skill is required. Therefore, yield losses due to handling must be expected. Furthermore, if completed IC packaged units are operated over wide temperature ranges, the materials mismatch and differential thermal expansion between the epoxy in contact with the semiconductor integrated circuit chip and the wire bonds can cause additional reliability problems and failure. As a result of the above problems, a need existed to provide a DIP package to overcome these problems.